1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to a semiconductor device having a pad polysilicon film for extracting source and drain electrodes or a nonvolatile semiconductor memory such as an EEPROM and a method of manufacturing the same.
2. Description of the Related Art
A technique of preventing an extraordinary resist pattern exposure due to the step between an element isolation region (field region) and an element formation region on forming a gate electrode wiring layer of a MOS transistor is disclosed in Japanese Parent Laid-Open No. 6-21054.
In the technique disclosed in Japanese Patent Laid-Open No. 6-21054, a first polysilicon film is formed on the entire surface of a silicon substrate having a field oxide film formed thereon. Thereafter, the first polysilicon film is polished to expose the field oxide film or leave the first polysilicon film having a predetermined thickness on the field oxide film, thereby planarizing the entire structure. When the first polysilicon film is polished to expose the field oxide film, a second polysilicon film is formed on the resultant structure, and a resist pattern is formed on the second polysilicon film. When the first polysilicon film having a predetermined thickness is left on the field oxide film, a resist pattern is formed on the planarized first polysilicon film. In any case, the resist pattern is formed across a field region and an active region (element formation region) surrounded by the field region. With this structure, an extraordinary resist pattern formation due to variations of the exposure focal position is prevented. Consequently, the width of the gate electrode wiring can be small-sized to almost the lowest exposure limit.
Japanese Patent Laid-Open. No. 6-349826 discloses use of almost the same technique as that of Japanese Patent Laid-Open No. 6-21054, to flush gate electrode layer in the element formation region and gate wiring layer in the field region are formed to the same level, thereby preventing etching into the substrate upon etching the gate electrode wiring layer.
Japanese Patent Laid-Open No. 4-62874 discloses a technique of preventing a mask displacement in gate electrode formation process, in which a gate electrode is deposited on the entire surface of a semiconductor substrate including an element isolation oxide film with a gate oxide film intervened there between. The surface of the gate electrode is planarized to the surface of the element isolation oxide film, so that the gate electrode is buried between adjacent element isolation oxide films.
Japanese Patent Laid-Open Nos. 5-335586 and 5-129621 disclose a technique to improve information storage capability of a nonvolatile semiconductor device, in which a polysilicon film serving as a floating gate is deposited on the entire surface of a semiconductor substrate having a filed oxide film. The polysilicon film is surface-polished to remove surface projections, and the polysilicon film is patterned into a floating gate having a predetermined shape.
Chemical mechanical polishing (CMP) as a polishing method is disclosed in Japanese Patent Laid-Open No. 62-102543 or 8-17831.
Japanese Patent Laid-Open No. 6-69352 discloses a technique in which gate electrodes formed on a gate oxide film are covered with an insulating film, a thick polysilicon film is formed to bury each gate electrode, and the surface of the polysilicon film is etched back to expose the upper surface of the insulating film which covers the gate electrodes. In this case, the polysilicon film is separated at a separation width equal to the width of the gate electrode upon etching back the polysilicon film, so that polysilicon pads (pad polysilicon films) are formed. More specifically, the polysilicon pads are formed such that the separation width between adjacent polysilicon pads equals the width of the gate electrode. For this reason, the width of the gate electrode can be small-sized to the lowest exposure limit.
A mask formation technique of forming a pattern having a width equal to or smaller than the exposure limit is disclosed in, e.g., Japanese Patent Laid-Open No. 1-114041. More specifically, a silicon oxide film is formed on a silicon substrate to be patterned, and a photoresist having a pattern with a width as small as the exposure limit is formed on the silicon oxide film. Subsequently, the silicon oxide film is anisotropically etched using the photoresist as a mask to form a silicon oxide film having the same width as that of the photoresist pattern. The silicon substrate is dipped in dilute hydrofluoric acid to make the width of the silicon oxide film smaller than the exposure limit, and the photoresist is removed. Thereafter, a new photoresist is form to bury the silicon oxide film. Etching is performed to expose the upper surface of the silicon oxide film. The silicon substrate is dipped again in dilute hydrofluoric acid to remove the silicon oxide film. With these processes, a mask having a pattern with a separation width smaller than the exposure limit is complete.
Japanese Patent Laid-Open No. 8-70120 discloses a technique in which a stopper portion consisting of an oxide film which covers the upper and side surfaces of a gate electrode is formed, and an impurity diffusion region consisting of polysilicon is formed between the gate electrode and the element isolation region through the stopper portion serving as a stopper.
Japanese Patent Laid-Open No. 6-13606 discloses a CMOS transistor having an SOI structure with two or more silicon layers, in which a common gate whose conductivity type changes from the first conductivity type to the second conductivity type is formed, and this gate is sandwiched between silicon layers having sources/drains with gate oxide films intervened.
Japanese Patent Laid-Open No. 6-21473 discloses a technique of attaining high integration of SRAM memory cells. In this technique, a polysilicon film is deposited on an element active region including a LOCOS region (field oxide film) with a first gate oxide film intervened. The polysilicon film is polished using the LOCOS region as a stopper to planarize the polysilicon film, thereby forming a lower gate. Next, a second gate oxide film and an upper gate are sequentially formed on the planarized LOCOS region and polysilicon film.
U.S. Pat. No. 5,422,289 discloses an art in which a field oxide film is formed through LOCOS process to fix an element active region, thereafter a gate electorde with its top face planarized and leading-out wirings from the gate and source/drain are formed.
U.S. Pat. No. 5,292,683 and U.S. Pat. No. 5,397,908 disclose an art in which isolation trench formed in a semiconductor substrate is filled, thereafter an element isolation structure with its upper portion projected on the surface of the substrate is formed by chemical mechanical polishing (CMP) process.
However, the following problems are posed in gate electrode formation.
In the technique disclosed in Japanese Patent Laid-Open No. 6-21054, the first polysilicon film can hardly be left to have a predetermined thickness on the field oxide film by polishing the first polysilicon film. In addition, when the first polysilicon film is polished using the field oxide film as a stopper, and thereafter, the second polysilicon film is formed on the resultant structure, two layers of polysilicon films constituting the gate electrode are formed. Projections are generated on the surface of the first polysilicon film due to a spontaneous oxide film or a transmutative substance generated upon polishing and left between the first and second polysilicon films. In addition, this technique requires an extra polishing process to the manufacturing processes and therefore cannot meet one of important requirements associated with manufacturing of the semiconductor device, i.e., reduction of the number of processes.
Along with progresses in micropatterning and high integration of semiconductor devices, pad polysilicon films for contact extraction are formed on the source/drain of a MOS transistor to mainly modify the positional accuracy of contact holes on she source/drain of the MOS transistor. This pad polysilicon films are electrically disconnected between the source and the drain, as a matter of course, and therefore must be separated on the gate electrode.
However, when the width of the gate electrode wiring layer is reduced to the exposure limit, the resist pattern used to separate the pad polysilicon films on the gate electrode has a width equal to or smaller than the exposure limit, so the pad polysilicon films are hard to be patterned by photolithography processes. For this reason, conventionally, the width of the gate electrode wiring pattern cannot be reduced to the exposure limit, thus impeding micropatterning of a semiconductor device.
The technique disclosed in Japanese Patent Laid-Open No. 1-114041 can be used to form the mask on the polysilicon film formed on the gate electrode wiring layer and form the pad polysilicon film having a width equal to or smaller than the exposure limit on the basis of the mask pattern. However, the cumbersome processes as described above are required to form the mask. Additionally, after formation of the pad polysilicon film., the process of removing the mask is also needed. In this case, addition of the mask formation and removing processes largely increases the number of manufacturing processes, resulting in a serious problem.
The technique disclosed in Japanese Patent Laid-Open No. 8-70120 can be used to fill the polysilicon film in a self-aligned manner between the gate on the element active region and the element isolation region. Actually, the gate is formed across the element active region and the element isolation region, so this technique cannot sufficiently cope with this situation.
The technique disclosed in Japanese Patent Laid-Open No. 8-70120 can be applied to only a semiconductor device having an SOI structure and therefore cannot be used for wide application purposes. In addition, the SOI structure does not allow use of gates of the same conductivity type.
Deep problems such as development of so called bird""s beak and penetration of field oxide into the element active region of the device occur in the process of the U.S. Pat. No. 5,422,289, in which an element isolation structure is constructed by a field oxide film formed by LOCOS process.
A complex step to form a sacrificial layer and then to remove the layer can not be omitted in the process disclosed in the U.S. Pat. No. 5,292,683 and U.S. Pat. No. 5,397,908 due to structural feature of the element isolation structure.
It is an object of the present invention to provide a semiconductor device which increases the process margin without being affected by close location of element isolation structures or any other underlying step and allows easy and proper formation of a desired gate electrode or various wiring layers, and a method of manufacturing the same.
It is another object of the present invention to provide a semiconductor device manufacturing method which can achieve further micropatterning of a gate electrode and realize high integration by properly patterning a pad polysilicon film even when the width of the gate electrode wiring layer of, e.g., a MOS transistor is reduced to the exposure limit.
It is still another object of the present invention to provide a semiconductor device manufacturing method which can achieve further micropatterning of a semiconductor device and realize high integration by patterning pad polysilicon films to have a separation width equal to or smaller than the exposure limit regardless of the width of the gate electrode wiring pattern of, e.g., a MOS transistor without any cumbersome processes or photolithography.
It is still another object of the present invention to provide a semiconductor device, i.e., a nonvolatile semiconductor memory which enables a storage deletion operation using a field shield element isolation structure in addition to a conventional storage deletion operation.
It is still another object of the present invention to provide a semiconductor device, i.e., a nonvolatile semiconductor memory in which an element isolation structure and a floating gate electrode are formed in a self-aligned manner to allow a large cell size reduction, and a method of manufacturing the same.
It is still another object of the present invention to provide a semiconductor device having a CMOS structure which uses no special semiconductor substrate such as an SOI structure to allow further integration on a flat structure with a small occupied area, and a method of manufacturing the same.
According to the present invention, there is provided a semiconductor device having a transistor with a gate, a source, and a drain formed in an element active region demarcated by non-LOCOS insulating device isolation blocks (non-LOCOS element isolation structures) on a semiconductor substrate, comprising at least two gates covered with insulating films and formed on the element active region to extend over the non-LOCOS insulating device isolation blocks, and a leading-out electrode filled between adjacent ones of the gates with the insulating films intervened, wherein upper surfaces of the gates are planarized at substantially the same level over the non-LOCOS insulating device isolation blocks and the element active region, and upper surfaces of the insulating films and an upper surface of the leading-out electrode are planarized at substantially the same level.
According to another aspect of the present invention, there is provided a semiconductor device, comprising a first step structure portion formed at a predetermined level from a surface of a reference layer, second step structure portions respectively formed on the first step structure portion and the reference layer and functioning as non-LOCOS insulating device isolation blocks for demarcating an element active region on the reference layer, and a first conductive film patterned on the element active region across at least the second step structure portion on the reference layer, wherein an upper surface of the first conductive film is planarized such that the upper surface of the first conductive film and an upper surface of the second step structure portion to formed on said first step structure portion are formed at substantially the same level.
According to still another aspect of the present invention, there is provided a semiconductor device comprising partially formed step structures, at least two first conductive films patterned on a step structure nonformation region and bestriding over the step structures, first insulating films covering the first conductive films, and a second conductive film filling between adjacent ones of the first conductive films with the first insulating films intervened, wherein upper surfaces of the first conductive films are planarized at substantially the same level over the step structures and the step structure nonformation region, and upper surfaces of the first insulating films and an upper surface of the second conductive film are planarized at substantially the same level.
According to still another aspect of the present invention, there is provided a semiconductor device comprising non-LOCOS insulating device isolation blocks for demarcating an element formation region on a semiconductor substrate, the non-LOCOS insulating device isolation block being formed by burying a first conductive film in a first insulating film, second conductive films filled, with intermediary of second insulating films, between adjacent ones of the non-LOCOS insulating device isolation blocks on the semiconductor substrate, capacitively coupled to the first conductive film through a side surface portion of the first insulating film, and separated into an island shape in the element formation region, and a third conductive film patterned into a strip shape on the second conductive film through a third insulating film and capacitively coupled to the second conductive film.
According to still another aspect of the present invention, there is provided a semiconductor device comprising non-LOCOS insulating device isolation blocks for demarcating an element formation region on a semiconductor substrate, the non-LOCOS insulating device isolation block being formed by burying a first conductive film in a first insulating film, a second conductive film filled, with intermediary of second insulating films, between adjacent ones of the non-LOCOS insulating device isolation blocks on the semiconductor substrate, and capacitively coupled to the first conductive film through a side surface portion of the first insulating film.
According to still another aspect of the present invention, there is provided a semiconductor device comprising a semiconductor region where a pair of first diffusion layers of a predetermined conductivity type are formed on surface regions, a first layer having a conductive film patterned on the semiconductor region with a first insulating film intervened, the first diffusion layers being formed on left and right sides of the conductive film, a second insulating film formed on an upper surface of the conductive film, a third insulating film covering side surfaces of the conductive film and the second insulating film and planarized such that an upper surface of the third insulating film and an upper surface of the second insulating film are formed on substantially the same plane, and a second layer patterned on the third insulating film including the upper surface of the second insulating film, in which a pair of second diffusion layers of a predetermined conductivity type are formed in regions on both sides of the second insulating film such that a region between the second diffusion layers opposes the conductive film through the second insulating film.
According to still another aspect of the present invention, there is provided a semiconductor device having first and second transistors which have a common gate, wherein the first transistor comprises the gate patterned on a semiconductor substrate with intermediary of a first gate insulating film, and first source and drain formed in surface regions of the semiconductor substrate on both sides of the gate, the second transistor comprises the gate, and second source and drain formed, on both sides of the gate, on a conductive film patterned on the gate with intermediary of a second gate insulating film formed on an upper surface of the gate, and an insulating interlayer is formed to cover side surfaces of the gate and the second gate insulating film and planarized such that an upper surface of the insulating interlayer and the upper surface of the second gate insulating film are on substantially the same plane, the conductive film being formed on the insulating interlayer including the upper surface of the second gate insulating film.
According to still another aspect of the present invention, there is provided a semiconductor device comprising a first insulating film filled in a groove formed in a semiconductor substrate, first conductive films patterned, with intermediary of a second insulating film, on at least a first insulating film nonformation region of the semiconductor substrate over the first insulating film nonformation region and the first insulating film, a third insulating film covering the first conductive film, a pair of diffusion layers formed in surface regions of the semiconductor substrate on both sides of the first conductive film, and a second conductive film filled, with intermediary of the third insulating film, between adjacent ones of the first conductive films and connected to the diffusion layer, wherein upper surfaces of the first conductive films are planarized across the nonformation region and the first insulating film on substantially the same plane, and an upper surface of the third insulating film and an upper surface of the second conductive film are planarized on substantially the same plane.
According to still another aspect of the present invention, there is provided a semiconductor device in which a transistor having a gate, a source, and a drain is formed in an element active region on a semiconductor substrate, comprising a non-LOCOS insulating device isolation block formed by filling a first insulating film in a groove formed in the semiconductor substrate to demarcate the element active region on the semiconductor substrate, a second insulating film covering the gate, and a leading-out electrode filled, with intermediary of the second insulating film, between adjacent ones of the gates, having an upper surface which is planarized to be on substantially the same plane as that of an upper surface of the second insulating film, and connected to the source or drain.
According to still another aspect of the present invention, there is provided a semiconductor device in which first and second transistors are stacked, wherein the first transistor has a first gate patterned on a semiconductor substrate with intermediary of a first gate insulating film, and first source and drain formed in surface regions of the semiconductor substrate on both sides of the first gate, an insulating interlayer having an upper surface is formed to cover the first gate, and the second transistor includes a conductive film patterned on the insulating interlayer, and has a second gate patterned on the conductive film through a second gate insulating film and second source and drain formed in the conductive film on both sides of the second gate.
According to still another aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate, an insulating film formed on the semiconductor substrate and having an opening for exposing a part of a surface of the semiconductor substrate, a lower electrode patterned on the insulating film to bury the opening and having a planarized upper surface, an upper electrode patterned on the lower electrode with intermediary of a dielectric film and capacitively coupled to the lower electrode, wherein another insulating film is formed to bury sides of the lower electrode, the dielectric film and the upper electrode, the another insulating film being planarized to have a top surface flushed with the top surface of the upper electrode.
According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising a first step for patterning a first insulating film on a reference layer, a second step for forming step structure portions respectively on the first insulating film and the reference layer, a third step for depositing a first conductive film on an entire surface of the reference layer including the step structure portions on the first insulating film to bury the step structure portions in the first conductive film, a fourth step for polishing the first conductive film using the step structure portions on the first insulating film as stoppers until surfaces of the step structure portions on the first insulating film are exposed, and the fifth step of patterning the first conductive film to form a predetermined pattern consisting of the first conductive film on the reference layer and the step structure portions.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising a first step for forming a groove portion in a semiconductor substrate serving as a reference layer, a second step for forming a step structure portion having a height smaller than a depth of the groove portion on a bottom surface in the groove portion, a third step for depositing a first conductive film on an entire surface of the semiconductor substrate including the groove portion to bury the step structure portion in the first conductive film, a fourth step for polishing the first conductive film using the semiconductor substrate around the groove portion as a stopper until a surface of the semiconductor substrate is exposed, and a fifth step for patterning the first conductive film to form a predetermined pattern of the first conductive film on the bottom surface in the groove portion and on the step structure portion.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming non-LOCOS insulating device isolation blocks in element isolation regions on a semiconductor substrate, forming a first insulating film on a surface of the semiconductor substrate in an element formation region surrounded and demarcated by the non-LOCOS insulating device isolation blocks, forming a first conductive film on an entire surface of the semiconductor substrate including the first insulating film to a thickness for burying the non-LOCOS insulating device isolation blocks, polishing the first conductive film to leave the first conductive film having a predetermined thickness on the non-LOCOS insulating device isolation block and planarize a surface of the first conductive films forming a second insulating film on the planarized first conductive film, patterning the second insulating film and the first conductive film to form patterns each consisting of the second insulating film and the first conductive film on the element formation region and the non-LOCOS insulating device isolation blocks, forming a third insulating film on a side surface of at least the first conductive film of the pattern and removing the first insulating film between the patterns, forming a second conductive film on an entire surface of the semiconductor substrate including a space between the patterns from which the first insulating film is removed to a thickness for burying the space between the patterns, and polishing the second conductive film until the second insulating film of the pattern is exposed.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming non-LOCOS insulating device isolation blocks in element isolation regions on a semiconductor substrate, forming a first insulating film on a surface of the semiconductor substrate in an element formation region surrounded and demarcated by the non-LOCOS insulating device isolation blocks, forming a first conductive film on an entire surface of the semiconductor substrate including the first insulating film to a thickness for burying the non-LOCOS insulating device isolation blocks, polishing the first conductive film to planarize a surface of the first conductive film using the non-LOCOS insulating device isolation blocks as stoppers, forming a second conductive film on an entire surface of the semiconductor substrate including the non-LOCOS insulating device isolation blocks, forming a second insulating film on the second conductive film, patterning the second insulating film and the first and second conductive films to form patterns each consisting of the second insulating film and the first and second conductive films on the element formation region and the non-LOCOS insulating device isolation blocks, forming a third insulating film on side surfaces of at least the first and second conductive films of the pattern and removing the first insulating film between the patterns, forming a third conductive film on an entire surface of the semiconductor substrate including a space between the patterns from which the first insulating film is removed, to a thickness to fill the space between the patterns, and polishing the third conductive film until the second insulating film of the pattern is exposed.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a transistor with a gate, a source, and a drain, comprising steps of covering the gate with an insulating film, forming a conductive film constituting a part of a leading-out electrode of the source or drain to cover an upper portion of the insulating film, and polishing the conductive film until the upper portion of the insulating film is exposed.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising steps of forming a first insulating film on a surface of a semiconductor substrate in an element formation region surrounded and demarcated by non-LOCOS insulating device isolation blocks formed in element isolation regions on the semiconductor substrate, forming a first conductive film on an entire surface of the semiconductor substrate including the first insulating film to a thickness for burying the non-LOCOS insulating device isolation blocks, removing a part of the first conductive film to leave the first conductive film having a predetermined thickness on the non-LOCOS insulating device isolation block and planarize a surface of the first conductive film, forming a second insulating film having an acid resistance on the planarized first conductive film, forming a third insulating film on the second insulating film, patterning the second and third insulating films and the first conductive film to form patterns each consisting of the second and third insulating films and the first conductive film on the element formation region and the non-LOCOS insulating device isolation blocks, forming a fourth insulating film having an acid resistance on a side surface of at least the first conductive film of the pattern and removing the first insulating film between the patterns, cleaning the third insulating film of the pattern to reduce a width of the third insulating film, forming a second conductive film on an entire surface of the semiconductor substrate including a space between the patterns from which the first insulating film is removed, to a thickness to bury the patterns, and polishing the second conductive film until the third insulating film of the pattern is exposed.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming a first insulating film on a surface of a semiconductor substrate in an element formation region surrounded and demarcated by non-LOCOS insulating device isolation blocks formed in element isolation regions on the semiconductor substrate, forming a first conductive film on an entire surface of the semiconductor substrate including the first insulating film to a thickness for burying the non-LOCOS insulating device isolation blocks, polishing the first conductive film using the non-LOCOS insulating device isolation blocks as stoppers to planarize a surface of the first conductive film, forming a second conductive film on an entire surface of the semiconductor substrate including the non-LOCOS insulating device isolation blocks, forming a second insulating film having an acid resistance on the second conductive film, forming a third insulating film on the second insulating film, patterning the second and third insulating films and the first and second conductive films to form patterns each consisting of the second and third insulating films and the first and second conductive films on the element formation region and the non-LOCOS insulating device isolation blocks, forming a fourth insulating film having an acid resistance on side surfaces of at least the first and second conductive films of the pattern and removing the first insulating film between the patterns, cleaning the third insulating film of the pattern using an acid solution to reduce a width of the third insulating film, forming a third conductive film on an entire surface of the""semiconductor substrate including a space between the patterns from which the first insulating film is removed, to a thickness for burying the patterns, and polishing the third conductive film until the third insulating film of the pattern is exposed.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising a first step for patterning a first conductive film on a semiconductor substrate with intermediary of a first insulating film and forming the first insulating film to cover the first conductive film to bury the first conductive film in the first insulating film, thereby forming non-LOCOS insulating device isolation blocks on the semiconductor substrate to demarcate an element formation region, a second step for forming a second insulating film on the semiconductor substrate in the element formation region, a third step for filling a second conductive film, with intermediary of the second insulating film, between adjacent ones of the non-LOCOS insulating device isolation blocks on the semiconductor substrate, a fourth step for sequentially depositing a third insulating film and a third conductive film on an entire surface of the non-LOCOS insulating device isolation blocks and the second conductive film, and a fifth step for patterning the third conductive film, the third insulating film, the second conductive film, and the second insulating film to form the third conductive film and the third insulating film into a strip shape and remove the second conductive film and the second insulating film between adjacent ones of the third conductive films.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising steps of forming a first insulating film on a step structure nonformation region on a semiconductor substrate having a step structure, forming a first conductive film on an entire surface including the step structure, polishing the first conductive film using an upper surface of the step structure as a stopper to planarize a surface of the first conductive film, patterning the planarized first conductive film to leave the first conductive film into a predetermined shape in the nonformation region, doping a first impurity in surface regions of the semiconductor substrate on both sides of the first conductive film to form a pair of first diffusion layers, forming a second insulating film on an entire surface including the step structure and the first conductive film, polishing the second insulating film using the upper surface of the first conductive film as a stopper to planarize a surface of the second insulating film, thermally oxidizing the upper surface of the first conductive film to form a third insulating film, patterning a second conductive film on the second insulating film including the third insulating film, and doping a second impurity in the second conductive film on both sides of a predetermined portion to form a pair of second diffusion layers except the predetermined portion on the second conductive film positioned on the third insulating film.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising steps of forming a first insulating film in a step structure nonformation region on a semiconductor substrate having a step structure, forming first conductive film on an entire surface including the step structure, polishing the first conductive film using an upper surface of the step structure as a stopper to planarize a surface of the first conductive film, forming a second conductive film on the planarized first conductive film, patterning the first and second conductive films into a predetermined shape to leave the first and second conductive films in the step structure nonformation region and leave only the second conductive film on the step structure, doping a first impurity in surface regions of the semiconductor substrate on both sides of the first and second conductive films to form a pair of diffusion layers, forming a second insulating film on an entire surface including the step structure and the second conductive film, polishing the second insulating film using an upper surface of the second conductive film to planarize a surface of the second insulating film, thermally oxidizing the upper surface of the second conductive film to form a third insulating film, patterning a third conductive film on the second insulating film including the third insulating film, and doping a second impurity in the third conductive film on both sides of a predetermined portion to form a pair of second diffusion layers except the predetermined portion on the third conductive film positioned above the third insulating film.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a first transistor and a second transistor having a second source and a second drain, the first and second transistors having a common gate, comprising steps of patterning the gate on a semiconductor substrate with intermediary of a first gate insulating film and doping a first impurity in surface regions of the semiconductor substrate on both sides of the gate to form a first source and a first drain, for constituting the first transistor, forming an insulating interlayer to cover the first transistor and polishing the insulating interlayer using the gate as a stopper to planarize a surface of the insulating interlayer, thermally oxidizing an exposed upper surface of the gate to form a second gate insulating film, and patterning a conductive film on the insulating interlayer including the second gate insulating film and doping a second impurity in the conductive film while masking a portion of the conductive film positioned above the second gate insulating film to form the second source and the second drain, thereby constituting the second transistor.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a first transistor and a second transistor having a second source and a second drain, the first and second transistors having a common gate, comprising the steps of forming non-LOCOS insulating device isolation blocks for demarcating an element active region on a semiconductor substrate, forming a first gate oxide film on a surface of the element active region, forming a first conductive film on an entire surface including the non-LOCOS insulating device isolation blocks, patterning the first conductive film to form the first conductive film into a predetermined shape in the element active region and to leave an upper portion of the first conductive film on the non-LOCOS insulating device isolation block, for forming the gate, doping a first impurity in surface regions of the semiconductor substrate on both sides of the gate in the element active region to form a first source and a first drain, for constituting the first transistor, forming an insulating interlayer to cover the first transistor and polishing the insulating interlayer using the gate as a stopper to planarize a surface of the insulating interlayer, thermally oxidizing an exposed upper surface of the gate to form a second gate insulating film, and patterning a second conductive film on the insulating interlayer including the second gate insulating film and doping a second impurity in the conductive film while masking a portion of the second conductive film positioned above the second gate insulating film to form the second source and the second drain, for constituting the second transistor.
According to still-another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising a first step for sequentially forming a first insulating film and a first conductive film on a semiconductor substrate, a second step for patterning the first conductive film, the first insulating film, and the semiconductor substrate to form a groove from the first conductive film to a predetermined depth of the semiconductor substrate, a third step for forming a second insulating film on an entire surface to cover an inner wall of the groove, a fourth step for forming a third insulating film on an entire surface including the groove, a fifth step for polishing the third insulating film to planarize the third insulating film until the first conductive film is exposed and filling the third insulating film in the groove, a sixth step for sequentially forming a second conductive film and a fourth insulating film on an entire surface including the planarized third insulating film, a seventh step for patterning the fourth insulating film, the second conductive film, the first conductive film, and the first insulating film to form a pattern consisting of the first insulating film, the first conductive film, the second conductive film, and the fourth insulating film into a predetermined shape in at least a groove nonformation region on the semiconductor substrate, an eighth step for forming a fifth insulating film on side surfaces of at least the first and second conductive films, a ninth step for forming a third conductive film on an entire surface including a space between the first and second conductive films adjacent to each other with intermediary of the fifth insulating film, and a tenth step for polishing the third conductive film to planarize the third conductive film until the fourth insulating film is exposed and filling the third conductive film, with intermediary of the fifth insulating film, between the first and second conductive films adjacent to each other.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising a first step for forming a first gate insulating film on a surface of a semiconductor substrate, a second step for patterning a first gate on the first gate insulating film, a third step for doping a first impurity in surface regions of the semiconductor substrate on both sides of the first gate to form a pair of first impurity diffusion layers, a fourth step for forming an insulating interlayer to cover the first gate and polishing the insulating interlayer to planarize a surface of the. insulating interlayer, a fifth step for patterning a conductive film on the insulating interlayer, a sixth step for forming a second gate insulating film on a surface of the conductive film, a seventh step for patterning a second gate on the second gate insulating film, and an eighth step for doping a second impurity in surface regions of the conductive film on both sides of the second gate to form a pair of second impurity diffusion layers.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising a first step for forming non-LOCOS insulating device isolation blocks for demarcating an element active region on a semiconductor substrate, a second step for forming a first gate insulating film on a surface of the element active region, a third step for forming a first conductive film on an entre surface including the non-LOCOS insulating device isolation blocks, a fourth step for patterning the first conductive film to form the first conductive film into a predetermined shape in the element active region with intermediary of the first gate insulating film and leave an upper portion of the first conductive film on the non-LOCOS insulating device isolation block, for forming a first gate, a fifth step for doping a first impurity in surface regions of the semiconductor substrate on both sides of the first gate in the element active region to form a pair of first impurity diffusion layers, a sixth step for forming an insulating interlayer to cover the first gate and polishing the insulating interlayer to planarize a surface of the insulating interlayer, a seventh step for pattering a second conductive film on the insulating interlayer including the second gate insulating film, an eighth step for forming a second gate insulating film on a surface of the second conductive film, a ninth step for forming a third conductive film on the second gate insulating film and patterning the third conductive film to form a second gate, and a tenth step for doping a second impurity in surface regions of the conductive film on both sides of the second gate to form a pair of second impurity diffusion layers.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising steps of forming an insulating film on a semiconductor substrate, forming an opening in the insulating film to expose a part of a surface, of the semiconductor substrate, forming a first conductive film on the insulating film to fill the opening, polishing a surface of the first conductive film to planarize the first conductive film, sequentially forming a dielectric film and a second conductive film on the planarized first conductive film, simultaneously patterning the second conductive film, the dielectric film, and the first conductive film into a capacitor shape, forming an insulating film to cover the second conductive film, the dielectric film and the first conductive film, respectively patterned into the capacitor shape, and polishing the insulating film using the second conductive film as a stopper to planarizi, until the surface of the second conductive film is exposed.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising steps of forming non-LOCOS insulating device isolation blocks in an element isolation region on a semiconductor substrate, forming a first insulating film on a surface of the semiconductor substrate in an element formation region surrounded and demarcated by the non-LOCOS insulating device isolation blocks, forming a first conductive film on an entire surface of the semiconductor substrate including the first insulating film to a thickness to bury the non-LOCOS insulating device isolation blocks, polishing the first conductive film using the non-LOCOS insulating device isolation blocks as stoppers to planarize a surface of the first conductive film, forming an underlayer consisting of a refractory metal on an entire surface of the semiconductor substrate including the non-LOCOS insulating device isolation blocks, forming a silicide film on the underlayer, forming a second insulating film on the silicide film, and patterning the second insulating film, the silicide film, the underlayer, and the first conductive film to form a pattern consisting of the first conductive film, the underlayer, the silicide film, and the second insulating film on the element formation region and the non-LOCOS insulating device isolation blocks.
According to the present invention, there is provided a method of deleting information from a semiconductor device, in use of the semiconductor device comprising non-LOCOS insulating-device isolation blocks for demarcating element active regions on a semiconductor substrate, wherein said device comprising a first conductive film buried in a first insulating film, a second conductive film formed into an island shape in the element active region and filled with intermediary of second insulating films, in the region between the non-LOCOS insulating device isolation blocks in the element active region between adjacent ones of the non-LOCOS insulating device isolation blocks, and a third conductive film formed on the second conductive film to oppose the second conductive film with intermediary of a third insulating film, wherein the second conductive film is capacitively coupled to the third conductive film through the third insulating film, and capacitively coupled to the first conductive film through a side surface portion of the first insulating film, the method comprising a step of applying a first voltage having a negative value to the first conductive film and a second voltage higher than the first voltage to the third conductive film to accumulate predetermined charges in the second conductive film, to shift a threshold value viewed from the third conductive film in a positive direction for deleting information.
According to still another aspect of the present invention, there is provided a semiconductor device having a transistor with a gate, a source, and a drain formed in an element active region demarcated by element isolation structures on a semiconductor substrate, comprising at least two gate structures each including said gate covered with insulating film and formed on the element active region to extend over the element isolation structures, and a leading-out electrode filled between adjacent ones of the gate structures, wherein upper surfaces of the gate structures are planarized at substantially the same level over the element isolation structures and the element active region, and upper surfaces of the insulating films and an upper surface of the leading-out electrode are planarized at substantially the same level.
According to still another aspect of the present invention, there is provided a semiconductor device comprising a first step structure portion made of a silicon film formed at a predetermined level from a surface of a semiconductor substrate, a second step structure portions respectively formed on the first step structure portion and on the semiconductor substrate, the second step structure portion on the semiconductor substrate serving as a field oxide film for demarcating element active regions, and conductive films patterned in the element active region to span over at least the second step structure portion on the semiconductor substrate, wherein upper surfaces of the conductive films are planarized at substantially the same level.
According to still another, aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising a first step for patterning a silicon film on a semiconductor substrate, a second step for applying field oxidation on the silicon film and the semiconductor substrate to form a field oxide film, a third step for depositing a conductive film on entire surface of the semiconductor substrate including the field oxide film on the silicon film, to bury the field oxide film within the conductive film, a fourth step for polishing the conductive film with using the field oxide film on the silicon film as a stopper until the surface of the field oxide film is exposed, and a fifth step for patterning the conductive film to form a predetermined pattern of the conductive film on the semiconductor substrate and on the field oxide film formed on the semiconductor substrate.
In the method of manufacturing the semiconductor device of the present invention, the first insulating film is patterned on the reference layer (e.g., a semiconductor substrate) in the first step. When a semiconductor substrate is used as the reference layer, an insulating layer patterned on the semiconductor substrate in formation of wells in surface regions of the semiconductor substrate may be commonly used as the first insulating film. In this case, the first insulating film is formed in a region including the scribing line of the semiconductor substrate. In the second step, using formation of the step structure portions (e.g., element isolation structures) on the reference layer, the step structure portions are formed not only on the reference layer but also on the first insulating film. In the third step, the first conductive film is deposited to bury the step structure portions. In the fourth step, the first conductive film is polished using the step structure portion on the first insulating film as a stopper until the surface of the step structure portion is exposed such that the upper surface of the first conductive film is flush with the upper surface of the step structure portion on the first insulating film. At this time, the conductive film which covers each step structure portion consists of a single layer of the first conductive film. In the fifth step, the first conductive film is patterned using a resist by photolithography. Since no step portions are present around the first conductive film, the resist can be prevented from being thinned due to step portions. In addition, since the first conductive film consists of a single layer of the conductive film, the conductive film can be easily and properly patterned into a desired shape.
In the method of manufacturing the semiconductor device of the present invention, a semiconductor substrate is used as the reference layer, and the first insulating film is formed on the scribing line region of the semiconductor substrate. When the scribing line region which does not contribute to formation of a semiconductor element in a normal state is used to planarize the polysilicon film, and the planarized polysilicon film is patterned. Since no steps are present in the periphery in patterning, the resist can be prevented from being thinned, and the gate electrode can be easily and properly patterned into a desired shape.
In the method of manufacturing the semiconductor device of the present invention, using the same technique disclosed in the above-described Japanese Patent Laid-Open No. 6-21054 or 8-349826, the pattern of the second insulating film and the first conductive film (or the first and second conductive films) in the element formation region, which is flush with that in the element isolation region and serves as, e.g., the gate electrode wiring layer, is formed. Next, the second conductive film (or the third conductive film) serving as, e.g., a pad polysilicon film formed on the entire surface to bury the pattern is polished using the second insulating film as the cap insulating film of the pattern as a stopper until the second insulating film is exposed. With these processes, the pattern of the second conductive film (or the third conductive film), i.e., the pad polysilicon film properly separated on the pattern of, e.g., the gate electrode wiring layer can be formed.
As described above, in the method of manufacturing the semiconductor device of the present invention, photolithography is not used to separate the second conductive film (or the third conductive film) serving as, e.g., a pad polysilicon film on the pattern of the second insulating film and the first conductive film (or the first and second conductive films) as, e.g., the gate electrode wiring layer. For this reason, the width of the pattern of the second insulating film and the first conductive film (or the first and second conductive films) as, e.g., the gate electrode wiring layer can be reduced to the substantial exposure limit in photolithography.
In the method of manufacturing the semiconductor device of the present invention, after a pattern consisting of the second and third insulating films and the first conductive film (or the second and third insulating films and the first and second conductive films) and serving as, e.g., a gate electrode pattern is formed, the fourth insulating film is formed on a side wall corresponding to at least the first conductive film (or the first and second conductive films) of the pattern. At this time, the portion of the first conductive film (or the first and second conductive films) is surrounded by the second and fourth insulating films. Next, the third insulating film on the second insulating film of this pattern is cleaned with an acid solution to make the width of the third insulating film smaller than that of the second insulating film and the first conductive film (or the second insulating film and the first and second conductive films). Thereafter, the second conductive film (or the third conductive film) serving as, e.g., a pad polysilicon film is formed on the entire surface of the semiconductor substrate including the space between the patterns from which the first insulating film is removed to a thickness for burying the pattern. The second conductive film (or the third conductive film) is polished until the third insulating film of this pattern is exposed. With these processes, the pattern of the second conductive film (or the third conductive film) serving as, e.g., a pad polysilicon film properly separated by the third insulating film can be formed.
More specifically, when the pattern consisting of the second and third insulating films and the first conductive film (or the second and third insulating films and the first and second conductive films) is formed such that the width of the pattern almost equals the exposure limit value, the width of the third insulating film cleaned with the acid solution is smaller than the exposure limit value. Therefore, the second conductive film (or the third conductive film) separated by the third insulating film and formed into a predetermined pattern has a separation width smaller than the exposure limit value.
As described above, according to the method of manufacturing the semiconductor device of the present invention, even when the width of the pattern serving as, e.g., the gate electrode wiring layer is reduced to the substantial exposure limit in photolithography, the second conductive film (or the third conductive film) can be separated without using photolithography to form, e.g., a pad polysilicon film having a separation width smaller than the exposure limit value.
In the semiconductor device of the present invention, the second conductive film filled between the adjacent element isolation structures is arranged to oppose the first conductive film, buried in the element isolation structure and functioning as a shield plate electrode, with intermediary of the side surface portion of the first insulating film which covers the first conductive film. In addition, the third conductive film is formed on the second conductive film with intermediary of the third insulating film. When the first conductive film is to be function as the shield plate electrode, the potential of the first conductive film is set at 0 (V), and the semiconductor substrate corresponding to the element isolation structure is fixed at 0 (V). With this arrangement, element isolation is attained. However, a voltage of 0 V or less can be applied to the first conductive film. When the second conductive film is to function as a floating gate electrode, and the third conductive film is to function as a control gate electrode (word line), a predetermined negative voltage is applied to the first conductive film to flow a tunnel current between the first conductive film and the second conductive film through the side surface portion of the first insulating film. With this arrangement, the first conductive film can be used not only as the shield plate electrode but also as a write/erase electrode.
In the method of manufacturing the semiconductor device of the present invention, in the first step and subsequent second step, the second insulating films serving as, e.g., tunnel insulating films are respectively formed on the (field shield) element isolation structures and the semiconductor substrate between the element isolation structures. Thereafter, in the third step, the second conductive film serving as, e.g., a floating gate electrode is filled, with intermediary of the second insulating film, on the semiconductor substrate between the adjacent element isolation structures. In the fourth step, the third insulating film serving as, e.g., a dielectric film and the third conductive film serving as, e.g., a control gate electrode (word line) are sequentially deposited on the entire surface of the element isolation structures and the second conductive film. In the fifth step, the third conductive film, the third insulating film, the second conductive film, and the second insulating film are patterned. At this time, the second conductive film opposes the third conductive film through the third insulating film and also opposes the first conductive film through the side surface portion of the first insulating film.
In the method of manufacturing the semiconductor device of the present invention, in the third step, the deposited second conductive film is surface-polished using the first insulating film of the element isolation structure as a stopper. Therefore, e.g., a floating gate electrode which is properly separated by the first insulating film of the element isolation structure can be formed in a self-aligned manner.
As described above, according to the method of manufacturing the semiconductor device of the present invention, photolithography is not used to separate the second conductive film serving as, e.g., a floating gate electrode on the pattern of the element isolation structure. For this reason, the width of the pattern of the first conductive film as the shield plate electrode of the element isolation structure can be reduced to the substantial exposure limit in photolithography.